Filter applications used in digital signal processing (DSP) systems require complex arithmetic capabilities. Efficient complex multiplications are increasingly needed in order to implement some of these filters. High-end DSP functions and finite impulse response (FIR) filters, for instance, require efficient multipliers. Integrated circuits (ICs) that are used to implement these DSP systems need to have cost-effective multipliers that can achieve all the required functions.
Generally, multipliers can be implemented either with embedded DSP blocks or dedicated blocks with customized multipliers, memory blocks, or logic elements in an IC. In most instances, memory based multipliers, also known as soft multipliers, are a flexible alternative to using DSP blocks. Generally speaking, soft multipliers utilize partial look-up tables (LUTs) to implement multiplication operations. Each address of the LUT can be used to represent a unique sum of a multiplication result. For instance, a memory block with a 5-bit wide input will be able to store 32 different combinations. All 32 possible combinations of a multiplicand summation are calculated and stored in the memory block as a LUT. Different configurations of multipliers can be generated by using different coefficient LUTs.
However, generally, the data width of memory blocks is limited and would limit the number of bits that can be stored in them. For example, if 18-bit memory blocks are used, two memory blocks will be needed to store a 20-bit multiplication result. In other words, more than one memory block will be needed to store results that are wider than the data width of the memory blocks used. Consequently, high-end filter applications with increasingly complex multiplications will require more and more memory blocks.
Therefore, it is desirable to have a technique to implement soft multipliers with fewer memory blocks. It is within this context that the invention arises.